This invention relates generally to a bus interface used for both cell and packet data transfer. More specifically, this invention relates to a bus interface for data transfer between a master and one or more slave devices and is capable of accommodating a large number of ports.
In conventional data communication systems, data is transferred over a bus connecting constituent component devices. Existing bus standards such as UTOPIA Levels 1 and 2 are used for ATM cell transfer, in either direction, between one or more Physical Layer (PHY or slaves) devices and an ATM Layer (Link Layer Processing or master) device. The UTOPIA Level 1 bus standard was designed for data transfer between one PHY device and an ATM Layer device. The UTOPIA Level 2 bus standard is an extension of UTOPIA Level 1 that supports data transfer between multiple PHY devices and an ATM Layer device. SCI-PHY is a PMC-Sierra proprietary bus interface similar to UTOPIA Level 2. POS-PHY Level 2 is also a PMC-Sierra proprietary bus interface similar to UTOPIA Level 2, but adapted for variable-length packet transfer.
In all of the UTOPIA-style bus standards described above, the Layer device (master) is the bus master, which controls data transfer to and from the PHY device or devices. On the transmit interface (Layer-to-PHY data transfer) of the bus, the Layer device polls the PHY device before sending data to the PHY device. The polled PHY device responds with a status signal to indicate if the FIFO queue of the PHY device has sufficient space to accept the data. Data transfer proceeds once the Layer device determines that the PHY device can accept the data.
On the receive interface (PHY-to-Layer data transfer) of the bus, the Layer device will poll the PHY devices to determine which PHY devices have data waiting to be to transferred. The Layer device will select a waiting PHY device, which then transfers the data to the Layer device.
Direct status indication may also be used instead of polling on the transmit and receive interfaces. With direct status indication, FIFO queue status information is communicated directly between the Layer device and the attached PHY device. While this scheme is simpler than polling, it requires dedicated signal lines between each PHY port and the Layer device.
Polling and direct status indication on the transmit and receive interfaces prove unsuitable for applications that require a large number of PHY device ports. As the number of PHY ports increases, the task of adequately polling individual ports becomes increasingly difficult and becomes impossible after a certain point. The requirement of dedicated signal lines for direct status indication makes it suitable for interfaces with a small number of PHY ports.
The existing interfaces also suffer from the limitation that at high bus clock rates the single-cycle decode-response timing requirements of the existing UTOPIA-style interfaces may not be met.
On the receive interface, a PHY device may begin a data transfer at the point when it is being deselected by the Layer device. This complicates the implementation of the Layer device as it must recover from this race condition and reselect the PHY.
On the transmit interface, polling and selection are coupled in the existing UTOPIA-style interfaces.
The existing interfaces also do not adequately handle a PHY device that employs an edge FIFO shared among its constituent ports. The edge FIFO for the transmit interface may become momentarily congested by a stream of short packets (or short remaining tail fragments of packets). The current interfaces do not allow the PHY device to backpressure the Layer device during these conditions by a supplemental mechanism to polling. A supplemental mechanism would allow polling information to reflect internal per-port buffer status independently from transient congestion conditions. On the receive interface, the edge FIFO may introduce additional latency between the time a PHY device is selected and when it can begin transferring data. These timing requirements and assumptions are not explicitly considered in the existing interfaces.
The existing bus interfaces lack a mechanism for integrating PHY devices with different address widths and different numbers of ports through the same bus interface.
Many multi-service applications require both cell and packet transfer over a common bus interface. Packet is used to indicate a data block of variable length whereas a cell is a data block with a fixed length. In general, a cell will have 48 bytes of data and 5 bytes for a header. The existing interfaces address either cell or packet transfer only and have not implemented combined cell and packet transfer within a unified framework.
It is, therefore, an object of this invention to provide an improved bus interface that can handle both cells and packets.
It is a further object of this invention to provide a bus interface that adequately handles PHY devices that employ an edge FIFO queue.
It is still a further object of this invention to provide a bus interface that can support a large number of logical ports and slave devices with different numbers of ports.
It is still a further object of this invention to provide a bus interface where polling operates independently from PHY selection.
These and other objects of the invention are provided in a new and improved bus interface. In general, the bus interface will be used in conjunction with one Link Layer Device and one or more PHY devices. A PHY device is a circuit that contains one or more logical PHY ports. The use of the term PHY without referring specifically to a PHY device or a PHY port means that the context applies to both PHY devices and PHY ports. The system is arranged such that the Link Layer device is connected to one side of the bus interface and the one or more PHY devices are connected to the other side of the bus interface. The Link Layer device is responsible for coordinating the transfer of data.
In operation, three processes are implemented through the bus interface: polling, selection and data transfer.
Polling
At each clock cycle, the Link Layer device polls a PHY port by presenting a PHY address over the address lines of the transmit and receive interfaces. The polled device responds two clock cycles later to indicate if a data transfer can take place. On the transmit interface, the polled PHY device asserts the packet available status if it can accept data of at least a minimum block size from the Link Layer device. On the receive interface, the polled PHY device asserts the packet available status if it has a block of data to send to the Link Layer device. For both the transmit and receive interfaces, the maximum block size that may be transferred depends on the application. For example, the maximum block size for ATM cells may be 52-bytes (excluding the header error control byte) while the maximum block size for packet fragments may be 256 bytes. The maximum block size is fixed at start-up, either inherently in the Link Layer and PHY-devices, or by programming through an external management interface.
On either the transmit or receive interface, the poll response from a PHY that is not currently selected refers to the packet available status of the PHY device if it were to be selected at the next transfer period. On the transmit interface, the packet available status of a currently selected PHY device, in response to a poll coincident with any other cycle after the start of a transfer within the current transfer period, refers to the packet available status for the next transfer period. On the receive interface, the packet available status of a currently selected PHY refers to the next transfer period if it is coincident with the start of a transfer or any other cycle thereafter within the current transfer period. In any case, the polled PHY returns a negative response if the packet available status is uncertain.
Selection
The transmit interface utilizes in-band PHY selection. This method involves the Link Layer device prepending the selected PHY port address to the transmitted data block, thereby decoupling polling from selection.
On the receive interface, the Link Layer device selects a PHY by placing the corresponding PHY address on the receive address line during the last cycle that the receive enable signal is high. The selected PHY may begin a block transfer anytime within the start window. The start window is from two through to a maximum number of cycles, inclusive, calculated after the receive enable signal goes low. The use of a start window gives a margin of flexibility for the PHY to respond with the block transfer after being selected. The address of the selected PHY port or PHY device, is sent at the beginning of the transfer period. At the end of the transfer period, the selected PHY deselects itself. Only one PHY can be selected at a time. If a PHY does not initiate block transfer within the start window as defined above, the PHY deselects itself until explicitly selected again by the Link Layer device.
A data transfer over the receive interface can be arbitrarily paused by the Link Layer device by holding the receive enable signal high. When the PHY device detects that the receive enable signal is high, two cycles later, the PHY device pauses the data transfer. The data transfer is resumed two cycles after the PHY device detects that the receive enable signal is low. The Link Layer device does not need to explicitly reselect the PHY before resuming the data transfer. However, the Link Layer device must ensure that another PHY has not been inadvertently selected.
If there are a large number of ports, then per-device polling and selection can be used. In this scheme, the PHY device acts as a proxy. If at least one of the constituent ports of the PHY device is ready to send a block of data, then the PHY device asserts the receive packet available signal. When the PHY device is selected, it prepends the address of the selected port to the data block. Per-device polling and selection and per-port polling and selection can co-exist in the same interface.
Data Transfer
Data is transferred to and from the PHY device in bursts referred to as block transfer periods. A block transfer period has a minimum length of 2 cycles and a maximum length that is set on start-up. In ATM applications, the maximum length of a transfer is typically set to the length of an ATM cell, including extensions for prepends and postpends. A transfer period ends when the end of a packet is reached or when the maximum transfer length has been reached. Cycles during which a transfer is paused do not count towards the maximum transfer limit. The selected PHY is deselected by default at the end of its transfer period.
To manage the situation where a PHY""s packet overhead processing capability has been exceeded, the selected PHY device can pause an on-going packet transfer from the Link Layer device. To accomplish this, a transmit ready signal is used. The transmit ready signal is held low to pause the transfer. The Link Layer device pauses two cycles after detecting a low transfer ready signal and resumes transmission two cycles after detecting a high transmit ready signal.
Alternatives to using a transfer ready signal include, a minimum gap between block transfers and timeout values.
Start of packet and end of packet signals are used on the transmit and receive interfaces to indicate the start and end of a packet, respectively. An error signal and a parity signal are also included in the transmit and receive interfaces.
Other objects and advantages of the invention will become clear from the following detailed description of the preferred embodiment, which is presented by way of illustration only and without limiting the scope of the invention to the details thereof.